1. Field of the Invention
The present disclosure relates to high density memory devices based on programmable resistive materials, including phase change materials like chalcogenides, and to methods for manufacturing such devices.
2. Description of Related Art
Programmable resistive materials, including phase change based materials, have been used in nonvolatile random access memory cells. Phase change materials, such as chalcogenides, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data.
Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched into either different solid phases or mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states.
The change from the amorphous to the crystalline state is generally a lower current operation, requiring a current that is sufficient to raise the phase change material to a level between a phase transition temperature and a melting temperature. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from a crystalline state to an amorphous state. The magnitude of the needed reset current can be reduced by reducing the volume of the active region in the phase change material element in the cell. Techniques used to reduce the volume of the active region include reducing the contact area between electrodes and the phase change material, so that higher current densities are achieved in the active volume, with small absolute current values through the phase change material element.
One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued 11 Nov. 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued 4 Aug. 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued 21 Nov. 2000.
Another memory cell structure under development, referred to sometimes as a “mushroom” cell because of the shape of the active region on the bottom electrode in a typical structure, is based on the formation of a small electrode in contact with a larger portion of phase change material, and then a usually larger electrode in contact with an opposite surface of the phase change material. Current flow from the small contact to the larger contact is used for reading, setting and resetting the memory cell. The small electrode concentrates the current density at the contact point, so that an active region in the phase change material is confined to a small volume near the contact point. See, for example, Ahn et al., “Highly reliable 50 nm contact cell technology for 256 Mb PRAM,” VLSI Technology 2005 Digest of Technical Papers, pages 98-99, 14 Jun. 2005; Denison, International publication No. WO2004/055916 A2, “Phase Change Memory and Method Therefore,” Publication Date: 1 Jul. 2004; and Song et al., United States Patent Application Publication No. US 2005/0263829 A1, “Semiconductor Devices Having Phase Change Memory Cells, Electronic Systems Employing the Same and Methods of Fabricating the Same,” published 1 Dec. 2005.
One prior art technique for making very small bottom electrodes, as described in the Ahn et al. publication, is referred to herein as a plug-in-via process, and includes forming a dielectric fill layer over circuitry for accessing the memory cell, etching vias in the dielectric fill layer to form an opening for making contact with the circuitry, and depositing electrode material into the via. The resulting structure is then planarized to expose the electrode material within the via. The phase change material is deposited and patterned in contact with the electrode. Although this technique is suitable for forming very small bottom electrode structures using a plug-in-via process, it has proved to suffer reliability and yield issues. For example, as described by Ahn et al., it has proven difficult to form reliable contact with the underlying access circuitry at the bottom of very small vias. This results in some cells in the array being permanently disconnected from the access circuits. See also, Horii, et al. “A Novel so Technology Using N-doped GeSbTe Films for Phase Change RAM,” 2003 Symposium on VLSI Technology, Digest of Technical Papers; Hwang, et al., “Full Integration and Reliability Evaluation of Phase-Change RAM Based on 0.24 um-CMOS Technologies,” 2003 Symposium on VLSI Technology, Digest of Technical Papers; Lai, et al., “OUM—180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications,” IEDM, 2001.
Furthermore, Ahn et al. have related that it is difficult to ensure in the plug-in-via process that the areas of the exposed tops of the plug electrodes are uniform after the planarizing step across a large array of such cells. Since the area of the top surface of the bottom electrode affects current density in the phase change material, and is a critical dimension for phase change cells of this type, variations in the contact area result in significant variations in operation of the cells in a single array.
Yet another problem arises in the formation of plug-in-via electrodes, because of the difficulty of uniformly filling vias. In particular, due to the dynamics of thin film deposition within small holes, the plug that results may include a void where the top of the via closes off before it has been completely filled below. Planarizing the structure may open the void, and create a hole in the top surface of the electrode plug. Such holes cause problems in the successful formation of a layer of phase change material over the electrode.
Another technology for making mushroom-type memory cells with pillar shaped bottom electrodes is described in our co-pending U.S. patent application Ser. No. 11/764,678; filed 18 Jun. 2007 (MXIC 1791-2).
Furthermore, the vias in the approach of Ahn et al. are made using lithographic processes which have characteristic minimum feature sizes, and typically result in vias that vary in diameter by as much as 5% of the minimum feature size. In some approaches, sidewalls are formed within the vias to reduce the cross-sectional area of the via used for electrode formation, reducing a critical dimension for the memory cell. The sidewall formation process involves conformal deposition of the sidewall material, having a uniform thickness around the walls of the via, and thus carrying the variation in size of the via into the critical dimension itself. Likewise, the pillars in the approach of U.S. patent application Ser. No. 11/764,678 are made by patterning photoresist using a lithographic process, and then trimming the photoresist elements in the pattern to reduce their dimensions below the minimum lithographic feature size. The trimmed photoresist element is used as an etch mask for formation of the bottom electrode and defines a critical dimension of the memory cell. This process also carries the variation in the minimum feature size of the photoresist elements into the critical dimension of the cell. Thus, for a lithographic minimum feature size of about 90 nm, which has a distribution of 5% across an array, the via diameters could vary as much as 4.5 nm. This 4.5 nm variation is carried according to the prior art techniques into the sub-lithographic feature size. So, a bottom electrode surface having a nominal diameter of 30 nm formed using the prior art techniques will vary in diameter across the array by as much as 4.5 nm, resulting in variation of the critical contact area of about 30% for a circular surface. This variation in the critical dimension of a programmable resistive memory cell reduces yield and complicates the technology for programming and reading the data in the cells.
Another problem with manufacturing very small dimension structures is alignment. When the structures are made using separate lithographic steps, the sizes of the structures, or of at least one of them, must be large enough to allow for alignment tolerances in the lithographic process. These requirements can restrict the flexibility in the design of the memory cells, and cause variation in the performance of the cells.
It is desirable therefore to provide a reliable method for manufacturing a memory cell structure with self-aligning and self-converging control over the critical dimensions of the bottom electrode and over the electrical integrity of connections to the bottom electrode, which will work with high density integrated circuit memory devices.